PREVAIL - A multi-hub Test and Experimentation Facility for edge AI hardware

The main objective of the PREVAIL project is to establish and start operating the core of a networked, multi-hub platform providing prototype chip fabrication capability, in advanced technology, to EU stakeholders for Artificial Intelligence (AI) applications. Four major European Research and Technology Organisations (RTOs) have set up this consortium to build on their advanced 300mm fabrication, design, and test facilities in a coordinated and complementary fashion to create a new multi-hub Test and Experimentation Facility for edge AI Hardware (TEF HW AI). In this new initiative, for the benefit of European stakeholders, the consortium will open and provide access, to advanced technologies that have been developed internally but that are not yet widely available commercially. In particular, the TEF HW AI will be providing access to advance non-volatile embedded memories (MRAM, OxRAM, FeRAM), 3D heterogeneous assembling (die to die, die to wafer, wafer to wafer), integrated photonics, RF connectivity and a unique connectivity testbed. This infrastructure will make available a trusted, non-discriminatory fabrication facility in Europe, capable of providing high-performance, low-power edge components and technologies to support the massive data-processing requirements of AI and the digital transformation.

3D PACKAGING TECHNOLOGIES:

Future system scaling will rely not only on further reduction of pitches but will also increasingly depend on the integration of heterogeneous parts using 3D and advanced packaging technologies. In a high performance, low power system the various functions, compute, memory, caches, IO are each realized in an optimized technology and integrated with 3D/advanced packaging technology. The system concept leverages the 3D interconnect technologies currently in development.

Various types of interconnects are needed, with pitches matching the bandwidth requirements of the system. Die-to-wafer solder-based micro-bumps or hybrid bonding (direct bonding) enable interconnect densities of 10e4cm^-2 while wafer-to-wafer hybrid bonding reaches 10e6cm^-2 interconnect densities.

A wider availability makes the offering prepared in PREVAIL very relevant as it allows early access to the EU semiconductor ecosystem, in particular for smaller companies and start-ups as the commercial offering grows in acceptance. Through-Silicon-Vias, used to deliver power directly to the standard cells, have been scaled to even smaller dimensions and pitches, enabling true 3D interconnections.

Fraunhofer IPMS will utilize its 300mm wafer-based Center Nanoelectronic Technologies CNT (1400 m² cleanroom) to focus on the Back End of Line segments of the Front End process technologies. 

The main goal is to close existing process gaps and to install the equipment upgrades necessary for (edge) AI applications, advanced packaging solutions as well as to create synergies on the platform for CMOS-based scalable prototypes, including new chips for neuromorphic or quantum computing devices.